UART¶
Summary
- UART (Universal Asynchronous Receiver/Transmitter) is a hardware peripheral that converts data between parallel form (inside the MCU) and serial form (on the wire), and is the oldest, simplest serial protocol still in everyday use on embedded boards.
- "Asynchronous" is the defining trait: there's no shared clock line between sender and receiver — both sides just have to agree in advance on a baud rate and frame format, and resynchronize at the start of every frame.
- UART itself only defines the electrical framing of each byte. It says nothing about addressing, multiple devices on a bus, or application-layer structure — that's left entirely to whatever protocol runs on top of it (or to point-to-point wiring, which is the common case).
Core Signals¶
A minimal UART connection needs only two signal wires plus a common ground — no clock, unlike SPI or I²C:1
| Signal | Direction | Purpose |
|---|---|---|
| TX (Transmit) | Output | Carries data out from this device |
| RX (Receive) | Input | Carries data in to this device |
| GND | — | Common voltage reference, required for the signal levels to mean anything |
Table 1. Minimal UART Wiring
TX connects to RX, not TX to TX
When wiring two UART devices together, cross the lines: Device A's TX goes to Device B's RX, and vice versa. Connecting TX-to-TX (a very common first-timer mistake) means neither side ever receives anything.
Frame Format¶
Each byte is sent as a self-contained frame, bracketed by start and stop bits so the receiver can detect where it begins and ends without a shared clock:2
| Field | Typical Value | Purpose |
|---|---|---|
| Start Bit | 1 bit, always low | Signals the beginning of a frame; this is what lets the receiver resynchronize each time |
| Data Bits | Usually 8 (5–9 possible) | The actual payload byte |
| Parity Bit | None / Even / Odd (optional) | A simple single-bit error-detection check |
| Stop Bit(s) | 1 or 2 bits, always high | Marks the end of the frame and gives the receiver a brief idle period before the next start bit |
Table 2. UART Frame Fields
Frame format is usually written in shorthand
A configuration like "8N1" means 8 data bits, No parity, 1 stop bit — by far the most common setting. You'll also see "8E1" (even parity) or "7O2" (7 data bits, odd parity, 2 stop bits) on older or more conservative systems.
Baud Rate¶
Baud rate is the number of signal symbols (here, bits) transmitted per second, and it's the one parameter both sides absolutely must agree on in advance:3
| Common Baud Rate | Typical Use |
|---|---|
| 9600 | Classic default, very reliable over longer/noisier wiring |
| 19200 / 38400 | Common step-up for debug consoles and simple sensors |
| 115200 | De facto standard for modern MCU debug/serial consoles |
| 230400 and above | High-throughput links (e.g. GPS modules at high update rates, some wireless modems) |
Table 3. Common UART Baud Rates
Baud rate mismatch doesn't fail cleanly
If both sides aren't within roughly a few percent of the same baud rate, the receiver samples bits at the wrong moments and produces garbled bytes or framing errors (below) — there's no handshake to catch this automatically, so it's a very common first debugging step with a new UART link.
Oversampling¶
To correctly detect the start bit and sample each data bit in the middle (where the signal is most stable), most UART hardware oversamples the incoming line, typically at 16x the configured baud rate:4
| Oversampling Rate | Trade-off |
|---|---|
| 16x | Standard choice on most MCU UART peripherals; good noise tolerance |
| 8x | Used when a higher baud rate is needed from a limited clock source; less tolerant of clock drift |
| 4x or lower | Rare, used only for very constrained timing budgets |
Table 4. UART Oversampling Rates
Voltage Levels & Standards¶
The same frame format is used across several different electrical standards, which are not directly compatible with each other:5
| Standard | Voltage Levels | Typical Use |
|---|---|---|
| TTL / CMOS UART | 0V = low, 3.3V or 5V = high | Chip-to-chip on the same board (MCU ↔ sensor, MCU ↔ MCU) |
| RS-232 | ±3V to ±15V, inverted logic | Legacy PC serial ports, some industrial/lab equipment |
| RS-485 | Differential signaling, supports multi-drop | Long-distance or noisy industrial links, allows multiple devices on one bus |
Table 5. UART Electrical Standards
Never wire RS-232 directly to a 3.3V MCU pin
RS-232's voltage swing and inverted polarity can damage a TTL-level UART pin. A level shifter / converter IC (e.g. MAX3232) is required to bridge the two.
Flow Control¶
Flow control lets one side signal the other to pause, preventing buffer overruns when one device is slower than the other:6
| Method | Mechanism |
|---|---|
| None | No flow control; the application must ensure the receiver can keep up |
| Hardware (RTS/CTS) | Two extra wires — Request to Send / Clear to Send — let either side assert "not ready" at the electrical level |
| Software (XON/XOFF) | Special in-band control bytes pause and resume transmission, at the cost of those byte values being unusable as data |
Table 6. UART Flow Control Methods
FIFO Buffering¶
Most modern UART peripherals include a small hardware FIFO (First-In, First-Out) buffer on both TX and RX, reducing how often the CPU needs to service an interrupt for every single byte:7
| Without FIFO | With FIFO |
|---|---|
| One interrupt per byte — high CPU overhead at high baud rates | One interrupt per several bytes (buffer threshold) — far less CPU overhead |
| Byte can be lost if the CPU is delayed even briefly | Several bytes of headroom before data is lost |
Table 7. FIFO vs. No FIFO
Common Error Conditions¶
Because UART has no shared clock and minimal error checking, a handful of error flags cover most real-world failure modes:2
| Error | Cause |
|---|---|
| Framing Error | The stop bit wasn't where it was expected — usually a baud rate mismatch or line noise |
| Parity Error | The received parity bit doesn't match the calculated parity of the data bits |
| Overrun Error | A new byte (or FIFO) arrived before the CPU read the previous one, so data was lost |
| Break Condition | The line is held low for longer than a full frame — often used deliberately as a reset/attention signal, but can also indicate a disconnected or misconfigured line |
Table 8. Common UART Error Flags
Useful Resources¶
- TI: UART Fundamentals — classic application note on UART operation
- NXP: Understanding UART — frame format and timing reference
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Texas Instruments. (n.d.). UART Fundamentals. https://www.ti.com/lit/an/slaa066a/slaa066a.pdf ↩
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NXP Semiconductors. (n.d.). Understanding UART. https://www.nxp.com/docs/en/application-note/AN10369.pdf ↩↩
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Texas Instruments. (n.d.). UART Fundamentals. https://www.ti.com/lit/an/slaa066a/slaa066a.pdf ↩
-
NXP Semiconductors. (n.d.). Understanding UART. https://www.nxp.com/docs/en/application-note/AN10369.pdf ↩
-
Texas Instruments. (n.d.). UART Fundamentals. https://www.ti.com/lit/an/slaa066a/slaa066a.pdf ↩
-
NXP Semiconductors. (n.d.). Understanding UART. https://www.nxp.com/docs/en/application-note/AN10369.pdf ↩
-
Texas Instruments. (n.d.). UART Fundamentals. https://www.ti.com/lit/an/slaa066a/slaa066a.pdf ↩