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SPI

Summary

  • SPI (Serial Peripheral Interface) is a synchronous, full-duplex serial bus where one clock line, driven by a single master, keeps every device on the bus bit-synchronized — unlike UART, there's no baud rate to agree on in advance.
  • SPI has no formal addressing scheme. Instead, the master selects exactly which slave is "listening" using a dedicated chip select line per device, which is also what makes SPI's pin count grow quickly with more slaves.
  • SPI was never formally standardized by a single body the way USB or PCIe were — it's a de facto standard, which is why clock mode (polarity/phase) and pin naming vary slightly between vendors and must always be checked against the datasheet.

Core Signals

A standard SPI bus uses four signal lines, though naming varies across manufacturers:1

Signal Common Alternate Names Purpose
SCLK SCK, CLK Clock, always driven by the master
MOSI SDO (master), COPI Master Out, Slave In — data from master to slave
MISO SDI (master), CIPO Master In, Slave Out — data from slave to master
SS / CS nCS, CSB, SSEL Chip/Slave Select — active-low line that enables one specific slave

Table 1. SPI Signal Lines

MOSI/MISO naming is being phased out

Because "master/slave" terminology is being retired industry-wide, newer datasheets increasingly use COPI (Controller Out, Peripheral In) and CIPO (Controller In, Peripheral Out) for the same two signals. Electrically and functionally they're identical to MOSI/MISO.

Full-Duplex Shift Register Operation

Every SPI transaction is really two shift registers — one in the master, one in the slave — wired into a single circular loop through MOSI and MISO:2

Step What Happens
1 Master pulls the target slave's CS line low, waking that slave up
2 On each clock edge, the master shifts one bit out on MOSI and simultaneously shifts one bit in on MISO
3 After 8 (or however many) clock edges, both shift registers have fully exchanged their contents
4 Master raises CS high again, ending the transaction

Table 2. SPI Shift Register Exchange

SPI is always full-duplex, even when you only care about one direction

Every byte sent is simultaneously a byte received, whether the application needs it or not. Reading a sensor register, for example, still requires the master to clock out dummy bytes on MOSI just to generate the clock edges needed to shift the response in on MISO.

Clock Polarity & Phase (SPI Modes)

Two independent settings, CPOL and CPHA, define when data is driven and sampled relative to the clock edge — both sides of a link must agree on the same mode:3

Mode CPOL CPHA Clock Idle State Data Sampled On
Mode 0 0 0 Low Leading (rising) edge
Mode 1 0 1 Low Trailing (falling) edge
Mode 2 1 0 High Leading (falling) edge
Mode 3 1 1 High Trailing (rising) edge

Table 3. The Four SPI Clock Modes

Wrong SPI mode is a classic silent failure

Unlike a baud rate mismatch on UART, a wrong SPI mode often doesn't produce an obvious error — it just silently shifts every sampled bit by one position, producing consistently garbled data. Always check the target device's datasheet for its required mode before wiring up a new part.

Multi-Slave Topologies

SPI supports more than one slave on the same bus, but — unlike I²C — it needs extra wiring to do it, in one of two ways:4

Topology Wiring Trade-off
Independent Chip Select One shared SCLK/MOSI/MISO, one dedicated CS line per slave Simple addressing (one CS = one slave), but pin count grows with slave count
Daisy Chain Slaves' MOSI/MISO are chained in series; shared CS and SCLK for all Pin count stays constant regardless of slave count, but every transaction must shift data through every device in the chain

Table 4. SPI Multi-Slave Topologies

Clock Speed

SPI has no fixed standard speed — it typically runs as fast as both the master and slave's electrical characteristics and PCB trace lengths allow:5

Typical Range Context
1–10 MHz Common for sensors, simple peripherals, breadboard/prototype wiring
10–50 MHz Common for flash memory, displays, ADCs/DACs on a clean PCB
50+ MHz Achievable on short, well-routed traces with compatible silicon (e.g. some external flash, high-speed ADCs)

Table 5. Typical SPI Clock Speeds

Variants: Dual, Quad & Octal SPI

Standard SPI uses one data line per direction. Several extensions reuse the same protocol structure but add more parallel data lines to boost throughput, common on NOR/NAND flash memory:6

Variant Data Lines Notes
Standard SPI 1 (MOSI) + 1 (MISO) Simultaneous bidirectional (full-duplex)
Dual SPI 2, shared direction 2x throughput, but half-duplex — both lines carry the same direction of traffic at once
Quad SPI (QSPI) 4, shared direction Very common on external flash chips for faster firmware boot/read
Octal SPI (OSPI) 8, shared direction Used where Quad SPI still isn't fast enough, e.g. high-density external flash

Table 6. SPI Throughput Variants

Dual/Quad/Octal SPI trade duplex for throughput

Standard SPI sends and receives at the same time on separate lines. Dual/Quad/Octal SPI instead use all available lines in one direction at a time, switching direction between phases of a transaction — more raw throughput, but no longer truly full-duplex.

Useful Resources

  1. NXP Semiconductors. (n.d.). SPI Block Guide. https://www.nxp.com/files-static/microcontrollers/doc/ref_manual/S12SPIV3.pdf ↩

  2. Texas Instruments. (n.d.). Understanding SPI. https://www.ti.com/lit/an/sloa294/sloa294.pdf ↩

  3. NXP Semiconductors. (n.d.). SPI Block Guide. https://www.nxp.com/files-static/microcontrollers/doc/ref_manual/S12SPIV3.pdf ↩

  4. Texas Instruments. (n.d.). Understanding SPI. https://www.ti.com/lit/an/sloa294/sloa294.pdf ↩

  5. NXP Semiconductors. (n.d.). SPI Block Guide. https://www.nxp.com/files-static/microcontrollers/doc/ref_manual/S12SPIV3.pdf ↩

  6. Texas Instruments. (n.d.). Understanding SPI. https://www.ti.com/lit/an/sloa294/sloa294.pdf ↩