PCIe¶
Summary
- PCIe (PCI Express) is the serial, point-to-point interconnect that replaced the old parallel PCI/PCI-X bus — instead of many devices sharing one wide, slow bus, each PCIe device gets its own dedicated high-speed link straight back to the system.
- Speed scales along two independent axes: generation (the signaling rate per lane, which roughly doubles each generation) and lane count (how many parallel serial lanes a link bundles together) — a x4 Gen4 link and a x8 Gen2 link can land at a similar bandwidth despite very different link widths.
- Like USB, PCIe is fully backward- and forward-compatible by design: a Gen5 card will still work in a Gen3 slot (just at Gen3 speed), and a x16 card works fine in a x4 slot (just at x4 bandwidth).
Lanes & Link Width¶
A PCIe lane is one differential transmit pair plus one differential receive pair — the smallest unit of a PCIe link:1
| Term | Meaning |
|---|---|
| Lane | One TX differential pair + one RX differential pair; simultaneously bidirectional |
| Link | One or more lanes bonded together between two devices |
| Link Width | Written as x1, x4, x8, x16, etc. — the number of lanes in a link |
| Slot Width vs. Electrical Width | A physical connector can be mechanically x16 but only electrically wired for x4 or x8, so a card may not get the full bandwidth the slot's size implies |
Table 1. PCIe Lane Terminology
Lanes scale linearly, generations scale the per-lane rate
Going from x1 to x16 multiplies bandwidth by 16. Going from Gen3 to Gen4 roughly doubles the per-lane rate. The two scale independently, which is why PCIe bandwidth is usually quoted as "Gen x Width" (e.g. "Gen4 x4").
Generational Roadmap¶
Each PCIe generation roughly doubles the raw per-lane transfer rate over the previous one:2
| Generation | Year | Per-Lane Rate (GT/s) | Encoding | x16 Bandwidth (approx, one direction) |
|---|---|---|---|---|
| PCIe 1.0 | 2003 | 2.5 | 8b/10b | ~4 GB/s |
| PCIe 2.0 | 2007 | 5.0 | 8b/10b | ~8 GB/s |
| PCIe 3.0 | 2010 | 8.0 | 128b/130b | ~16 GB/s |
| PCIe 4.0 | 2017 | 16.0 | 128b/130b | ~32 GB/s |
| PCIe 5.0 | 2019 | 32.0 | 128b/130b | ~64 GB/s |
| PCIe 6.0 | 2022 | 64.0 | PAM4 + FLIT | ~121 GB/s |
| PCIe 7.0 | 2025 | 128.0 | PAM4 + FLIT | ~242 GB/s |
Table 2. PCIe Generational Speed Roadmap
GT/s isn't the same as GB/s
The per-lane rate is quoted in GT/s (gigatransfers per second), which includes encoding overhead. Usable data throughput is always lower than the raw GT/s figure — that's exactly what the encoding efficiency (below) accounts for.
Encoding & Signaling¶
PCIe adds encoding overhead to the raw signal to keep enough transitions on the wire for clock recovery, and to let the receiver detect errors:3
| Encoding | Used In | Overhead | Notes |
|---|---|---|---|
| 8b/10b | Gen1, Gen2 | 20% | Simple, well-understood, but costly at higher rates |
| 128b/130b | Gen3, Gen4, Gen5 | ~1.5% | Far more efficient; the big reason Gen3's real-world throughput jump was larger than Gen2's raw rate alone suggests |
| PAM4 signaling | Gen6, Gen7 | — | Encodes 2 bits per symbol (4 voltage levels instead of 2), doubling throughput without doubling raw signaling frequency |
| FLIT mode (Flow Control Unit) | Gen6, Gen7 | — | Fixed-size packet framing required to make PAM4's higher error rate manageable, replacing the older variable-length packet framing |
Table 3. PCIe Encoding Schemes
Topology¶
A PCIe system is organized as a tree, not a shared bus — every device ultimately connects back toward one root complex:4
| Term | Role |
|---|---|
| Root Complex (RC) | Connects the CPU/memory subsystem to the PCIe hierarchy; the "trunk" of the tree |
| Endpoint | A leaf device — a GPU, NVMe SSD, NIC, etc. |
| Switch | Fans a single upstream link out into multiple downstream links, letting more endpoints attach than the root complex has native ports for |
| Bridge | Connects a PCIe hierarchy to a different bus type (e.g. legacy PCI) |
Table 4. PCIe Topology Roles
Link Training & Negotiation¶
Before any data flows, two connected PCIe devices automatically negotiate the best link both sides support — this is why mismatched hardware "just works," only slower:5
| Step | What Happens |
|---|---|
| Detect | Devices sense that a link partner is electrically present |
| Polling | Devices exchange training sequences to lock bit/symbol timing |
| Configuration | Devices agree on final link width and lane ordering/polarity |
| L0 (Active) | Normal operating state once training completes |
Table 5. Simplified Link Training Flow
This is why a x16 card still works in a x4 slot
Link training always negotiates down to whatever both ends can support — fewer lanes, a lower generation, or both. The link simply runs at the lowest common denominator rather than failing.
Configuration Space¶
Every PCIe function exposes a standardized block of registers the system uses to discover and configure it — this is how an OS enumerates PCIe devices at boot without needing device-specific wiring:6
| Region | Size | Purpose |
|---|---|---|
| PCI-Compatible Header | First 256 bytes | Legacy-compatible fields: Vendor ID, Device ID, Class Code, BARs |
| Extended Configuration Space | Up to 4 KB total | PCIe-specific capability structures (power management, error reporting, etc.) |
| BAR (Base Address Register) | Part of the header | Tells the system how much address space the device needs and where to map it |
Table 6. PCIe Configuration Space
Common Form Factors¶
The same PCIe link can be exposed through several different physical connectors depending on the device type:7
| Form Factor | Typical Use |
|---|---|
| Add-in Card (AIC) | GPUs, capture cards, add-in NICs — plugs into a standard slot |
| M.2 | Compact NVMe SSDs and Wi-Fi/Bluetooth modules; shares the connector with SATA-based M.2 drives, so matching the right key/mode matters |
| U.2 / U.3 | Enterprise/server NVMe SSDs, hot-swappable, 2.5" drive form factor |
| OCuLink | External or internal cabled PCIe, common for eGPU enclosures and some server backplanes |
Table 7. PCIe Physical Form Factors
Useful Resources¶
- PCI-SIG — the organization that owns and publishes the PCIe specifications
- PCI-SIG Specifications — official spec library and version history
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PCI-SIG. (n.d.). PCI Express Base Specification. https://pcisig.com/specifications ↩
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PCI-SIG. (n.d.). PCI Express Specifications Overview. https://pcisig.com/specifications ↩
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PCI-SIG. (n.d.). PCI Express Base Specification. https://pcisig.com/specifications ↩
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PCI-SIG. (n.d.). PCI Express Base Specification. https://pcisig.com/specifications ↩
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PCI-SIG. (n.d.). PCI Express Base Specification. https://pcisig.com/specifications ↩
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PCI-SIG. (n.d.). PCI Express Base Specification. https://pcisig.com/specifications ↩
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PCI-SIG. (n.d.). PCI Express Specifications Overview. https://pcisig.com/specifications ↩