IC Packaging¶

How IC Packages Are Classified¶

There are several ways to classify a package, and these classifications overlap.

Through-Hole Packages¶

Through-hole packages were among the earliest mass-produced IC package families. Their leads pass through holes drilled into the PCB and are soldered on the opposite side.

They are physically larger than modern surface-mount packages, but they remain useful for prototyping, education, legacy systems, high-voltage applications, and situations where mechanical robustness matters.

Dual In-Line Package (DIP)¶

The DIP places two parallel rows of leads along the sides of a rectangular package.

It became one of the most important early IC package formats because it was inexpensive, easy to manufacture, easy to insert into a PCB, and easy to handle manually.

Single In-Line Package (SIP or SIPP)¶

A package with one row of leads.

SIPs were used for memory modules, resistor networks, power devices, and various older integrated circuits.

Zig-Zag In-Line Package (ZIP)¶

A variation of an in-line package in which the leads alternate in a zig-zag arrangement.

The geometry allowed more pins without making the package excessively wide.

Pin Grid Array (PGA)¶

A package with pins arranged in a two-dimensional grid on its underside.

PGAs were historically important for CPUs and other high-pin-count devices before BGA became dominant.

Small-Outline Packages¶

Small-outline packages moved IC packaging from through-hole assembly toward surface-mount assembly.

They use metal leads extending from the package body and are soldered directly onto PCB pads.

Small-Outline Integrated Circuit (SOIC)¶

A rectangular surface-mount package with gull-wing leads on two sides.

SOIC became one of the most widely used general-purpose SMT IC packages.

Small-Outline Package (SOP)¶

A general family of small surface-mount packages with leads on two sides.

SOIC is one of the most common members of the broader SOP family.

Thin Small-Outline Package (TSOP)¶

A thinner small-outline package designed for applications where vertical space is restricted.

It became particularly common in memory devices.

Thin Shrink Small-Outline Package (TSSOP)¶

A smaller-pitch, thinner evolution of SOIC/SOP packaging.

Shrink Small-Outline Package (SSOP)¶

A smaller-pitch SOP family intended to increase pin density without moving to an area-array package.

Leaded Quad Packages¶

Quad packages place leads on all four sides of the package.

Quad Flat Package (QFP)¶

A square or rectangular package with gull-wing leads extending from all four sides.

QFPs became extremely common for microcontrollers, DSPs, ASICs, and other medium-to-high I/O devices.

Quad Flat No-Lead Package (QFN)¶

A leadless package with electrical contacts exposed around the underside perimeter.

Many QFN packages also include a large exposed center pad connected to ground or a thermal path.

Dual Flat No-Lead Package (DFN)¶

A two-sided leadless package similar in concept to QFN but with contacts primarily on two sides.

Leadless Packages¶

Leadless packages remove conventional protruding leads and expose contacts underneath or around the bottom of the package.

They became important because removing long leads reduces package size and parasitic inductance.

Land Grid Array (LGA)¶

An array of flat metal contacts arranged on the underside of the package.

Unlike BGA, an LGA package normally has lands rather than solder balls.

Ball Grid Array (BGA)¶

A package using an array of solder balls underneath the package.

Unlike perimeter-leaded packages, BGA connections can use the entire underside of the package.

Chip-Scale Packages¶

Chip-Scale Package (CSP)¶

A package whose footprint is approximately the same size as the die. A commonly used IPC definition limits a CSP to a package area no greater than approximately 1.2 times the die area.

CSP exists because conventional package bodies and leadframes can become much larger than the silicon they contain.

Wafer-Level Chip-Scale Package (WLCSP)¶

A package fabricated largely at wafer level before individual devices are singulated.

The package can be almost exactly the size of the silicon die.

System-in-Package¶

System-in-Package (SiP)¶

A system-in-package integrates multiple dies and/or passive components inside one package — for example, a processor, memory, RF circuitry, power management, and passive components together.

The key idea is that the system is assembled at the package level rather than placing every component independently on the PCB.

Multi-Chip Package (MCP)¶

A package containing multiple semiconductor dies. A common example is combining memory dies or combining memory with a controller.

Multi-Chip Module (MCM)¶

An assembly containing multiple bare or packaged dies mounted on a common substrate.

MCMs were an important predecessor to modern SiP and advanced packaging.

Package-in-Package (PiP)¶

One packaged IC is placed inside or integrated with another package.

Package-on-Package (PoP)¶

Multiple packages are vertically stacked, with one package soldered directly on top of another — a common arrangement is a processor package underneath a memory package.

Direct Die and Bare-Die Packaging¶

Chip on Board (COB)¶

In COB, the bare die is mounted directly on a PCB and connected using wire bonds or another interconnection method. The die is then protected using encapsulation.

Chip on Glass (COG)¶

A bare die mounted directly onto a glass substrate — commonly associated with display driver electronics, where the connections are made directly to the display glass.

Chip on Flex / Chip on Film (COF)¶

A die attached directly to a flexible circuit or film — in the display industry this is specifically called COF (Chip-on-Film), where the driver IC sits on a flexible film attached to the display and can fold behind it.

Tape Automated Bonding (TAB)¶

A technology in which the die is connected to conductive traces on a flexible tape.

TAB became particularly important for display driver ICs and high-volume electronics.

Beam-Lead Packages¶

Beam-Lead Package¶

A bare semiconductor die with extended metal leads projecting directly from the die.

Beam-lead technology was an early attempt to eliminate bulky conventional package structures.

Ceramic and Hermetic Packages¶

Metal Can Package¶

A cylindrical metal package derived from early transistor packaging. Typical examples include TO-style metal packages.

Ceramic Package¶

Ceramic packages use materials such as alumina or other engineered ceramics.

Ceramic Flat Package¶

A flat ceramic package with leads extending from the sides — historically important in military and aerospace electronics.

Ceramic Quad Flat Package (CQFP)¶

A ceramic version of a quad flat package.

Hermetic Package¶

A hermetic package forms a sealed environment around the semiconductor — used where moisture, gases, contaminants, or long-term environmental exposure must be tightly controlled.

Power IC Packages¶

Power semiconductor packages must solve a different problem from ordinary logic ICs: heat and current can dominate the package design.

TO Package¶

The TO (Transistor Outline) family includes numerous mechanical package styles that have also been used for diodes, regulators, power transistors, sensors, and other semiconductor devices. Examples include TO-18, TO-92, TO-220, TO-247, and many others.

Power QFN¶

A QFN-style package optimized for power devices — a large exposed metal pad provides a low-resistance thermal path into the PCB.

Power BGA¶

A BGA architecture adapted for devices where both electrical current and thermal transfer are important, combining BGA's high I/O density with the added thermal/current-handling design considerations of a power device.

RF and Microwave Packages¶

RF packages must minimize parasitic capacitance and inductance while controlling electromagnetic behavior.

RF QFN¶

A leadless package commonly used for RF transceivers, LNAs, mixers, switches, and other microwave circuits.

RF Ceramic Package¶

Ceramic packages can provide excellent electrical characteristics and environmental stability for demanding RF applications.

Leaded Chip Carriers¶

Ceramic Leadless Chip Carrier (CLCC)¶

A ceramic leadless package with contacts around the perimeter, historically important in military, aerospace, and older EPROM-style applications.

Plastic Leaded Chip Carrier (PLCC)¶

A square package with J-shaped leads underneath its edges.

PLCC packages were widely used for microcontrollers, memory, logic, and programmable devices.

Array Packages¶

Column Grid Array (CGA)¶

An area-array package using columns as the external interconnect, similar to BGA but using compliant solder columns rather than conventional solder balls — the columns can absorb some of the mechanical mismatch between the package and PCB.

Wafer-Level and Redistribution Packages¶

Wafer-Level Packaging (WLP)¶

A packaging approach in which significant portions of the packaging process are performed while the dies are still part of a wafer.

Traditional packaging generally follows:

Wafer
 ↓
Dice
 ↓
Individual Die
 ↓
Package

WLP instead performs packaging operations before final singulation:

Wafer
 ↓
Wafer-Level Packaging
 ↓
Singulation
 ↓
Finished Packages

Redistribution Layer (RDL)¶

An RDL reroutes the original die pads to different locations, allowing the external connection pattern to be changed without redesigning the silicon.

RDL is a fundamental technology behind WLCSP and fan-out packaging.

Fan-Out Packaging (FOWLP)¶

Fan-out packaging places the external connections outside the original die footprint — the term fan-out refers to the electrical connections spreading outward from the die.

Panel-Level Packaging (PLP)¶

A variation of fan-out packaging in which packaging is performed on a large rectangular panel instead of a circular wafer.

Flip-Chip Packaging¶

Flip Chip¶

In flip-chip assembly, the die is flipped upside down and electrically connected to the substrate using bumps.

This is fundamentally different from wire bonding, where the die remains face-up and wires extend from the die to the package.

Underfill deserves a special mention: it isn't itself a package type, but is an important part of many flip-chip packages. A polymer fills the space beneath the die and around the bumps, helping distribute mechanical stress.

Advanced Substrate Packages¶

Organic Substrate Package¶

Many modern BGAs use multilayer organic substrates to route signals between the die and package balls.

Build-Up Substrate¶

A package substrate constructed from multiple fine-pitch wiring layers.

2.5D Packaging¶

Silicon Interposer¶

A silicon interposer is a piece of silicon containing extremely dense wiring that connects multiple dies. The dies sit next to one another rather than directly on top of one another.

2.5D Integrated Circuit¶

A 2.5D package places multiple dies side by side on an interposer or high-density substrate — sitting between traditional 2D packaging and true 3D die stacking.

3D IC Packaging¶

3D Die Stacking¶

3D packaging vertically stacks semiconductor dies, creating electrical connections vertically through the stack rather than only side-by-side.

Through-Silicon Via (TSV)¶

A TSV is a vertical electrical connection passing through silicon, used to connect vertically stacked dies — fundamental to many 3D packaging architectures.

Hybrid Bonding¶

Hybrid bonding directly connects fine-pitch metal structures and surrounding dielectric surfaces between dies, achieving much finer interconnect density than traditional solder bumps.

High-Bandwidth Memory Packaging¶

High Bandwidth Memory (HBM)¶

HBM stacks multiple memory dies vertically and connects them using dense vertical interconnects, commonly integrated with a processor or accelerator using a 2.5D interposer architecture.

Chiplet Packaging¶

Chiplet¶

A chiplet is a relatively small die designed to be integrated with other dies inside a package — instead of manufacturing an entire complex processor as one giant die, functionality is divided across multiple dies.

Chiplet Interconnect¶

Chiplets require an electrical interface between dies. Modern systems may use proprietary interfaces or standards such as UCIe for die-to-die communication.

The physical interconnect may be implemented using organic substrate traces, silicon interposers, bridges, RDL, hybrid bonding, or microbumps.

Embedded Die Packaging¶

Embedded Die Package¶

An embedded-die package places one or more dies inside the package substrate or molding structure rather than simply mounting them on top.

Optical and Photonic Packages¶

Optoelectronic Package¶

Optoelectronic packages integrate electronic dies with optical components such as lasers, photodiodes, optical fibers, or photonic circuits.

Photonic Integrated Circuit Package¶

A package designed specifically to connect optical and electrical interfaces to a photonic integrated circuit.

Sensor and MEMS Packages¶

MEMS Package¶

MEMS devices often require packages that provide a controlled mechanical or environmental interface — examples include accelerometers, gyroscopes, pressure sensors, microphones, and other inertial sensors.

Wafer-Level MEMS Package¶

A MEMS structure is sealed or capped at wafer level before the devices are separated.

Memory Packaging¶

Stacked Memory Package¶

Multiple memory dies are vertically stacked to increase capacity without increasing PCB footprint.

MCP Memory Package¶

An MCP can combine different memory technologies or multiple memory dies inside one package — common combinations historically include NAND and RAM.

Package Technologies by Interconnection Method¶

The physical package name and the internal die connection method are separate concepts.

Wire Bonding¶

Wire bonding connects die pads to package leads or a package substrate using very fine wires. Common wire materials include gold, copper, and aluminum depending on the application and process.

Package Construction Materials¶

Plastic / Molded Package¶

The die and its connections are encapsulated in an epoxy molding compound — the dominant construction for many low-cost consumer and industrial ICs.

Epoxy Molded Compound (EMC)¶

EMC is used to encapsulate semiconductor dies and protect internal structures. It is not itself a package outline, but it is fundamental to many plastic semiconductor packages.

System-on-Package¶

System-on-package describes architectures where substantial system functionality is implemented inside the package — conceptually broader than simply placing multiple identical dies together, and distinct from SiP in that it emphasizes system-level design happening at the package level rather than just multi-die integration.

Why So Many Package Types Exist¶

There is no universally "best" IC package because every application has different requirements.

Size — Wearables and smartphones need extremely small packages, driving technologies such as WLCSP, FOWLP, CSP, QFN, SiP, and 3D stacking.

I/O Count — A simple temperature sensor may need only a few connections, while a GPU can require thousands. Low-I/O devices can use SOT, DIP, SOIC, or QFN; high-I/O devices may require BGA, FCBGA, LGA, 2.5D interposers, or 3D packaging.

Thermal Performance — As semiconductor power increases, the package must remove more heat, driving exposed-pad QFN, Power QFN, BGA, FCBGA, ceramic packages, heat spreaders, 2.5D packages, and advanced 3D thermal solutions.

Electrical Performance — High-speed signals cannot tolerate excessive parasitic inductance and capacitance, favoring QFN, LGA, BGA, flip chip, RDL, silicon interposers, and hybrid bonding.

Cost — Consumer electronics may require millions of inexpensive packages, favoring plastic packages, leadframes, wire bonding, and high-volume WLP. Specialized aerospace or high-reliability electronics may instead justify ceramic packages, hermetic packages, and specialized substrates.

Reliability — Different environments require different packaging. A consumer device may prioritize low cost and small size, while an aerospace device may prioritize hermetic sealing, temperature stability, and long-term reliability.

Manufacturing — A package must also be compatible with the manufacturing equipment available to assemble it, creating a tradeoff between package performance, package complexity, and manufacturing cost.

Package Evolution¶

The broad evolution of IC packaging can be summarized as:

DIP / Through-Hole
    ↓
SOP / SOIC
    ↓
QFP / PLCC
    ↓
QFN / LGA
    ↓
BGA
    ↓
CSP / WLCSP
    ↓
Flip-Chip
    ↓
Fan-Out
    ↓
SiP / Multi-Chip
    ↓
2.5D Interposer
    ↓
3D Stacking
    ↓
Chiplets / Advanced 3D Integration

This is not a strict replacement chain. Older packages continue to exist because they remain advantageous for particular cost, reliability, assembly, or electrical requirements.

Package Selection Guide¶

Important Package Terminology¶

Die — The actual piece of semiconductor containing the integrated circuit.

Package — The structure surrounding and connecting the die.

Lead — A conductive external connection extending from a package.

Pad — A flat conductive contact used for bonding or soldering.

Ball — A solder connection used by BGA-style packages.

Bump — A small conductive structure used for flip-chip or other advanced interconnections.

Substrate — A package-level circuit board that routes signals between the die and external package connections.

Interposer — A high-density intermediate layer used to connect dies to one another or to the package substrate.

RDL — Redistribution layer that moves electrical connections from their original die locations to new external locations.

TSV — Through-silicon via used for vertical electrical connections through silicon.

Underfill — Material placed beneath flip-chip dies to improve mechanical reliability.

Heat Spreader — A metal structure that distributes heat from the die over a larger area.

Heat Sink — An external thermal structure that removes heat from the package.

Mold Compound — Protective material surrounding the die and internal connections.

Hermetic Seal — A package seal designed to prevent significant exchange of gases or moisture with the environment.

Useful Resources¶

• IEEE Technology Navigator — Chip-Scale Packaging — overview of CSP technology and package architectures
• SK hynix — Semiconductor Packaging — overview of conventional, wafer-level, flip-chip, RDL, and TSV packaging
• SK hynix — Wafer-Level Packaging — fan-in, fan-out, RDL, flip-chip, and TSV technologies
• Analog Devices — Flip-Chip and Chip-Scale Packaging — CSP and flip-chip fundamentals
• Siemens — IC Package Types — overview of conventional and advanced package types